
`include "defines.v"

module ie (
    input  wire              rst,
    
    input  wire [31 : 0]     inst,
    input  wire [2  : 0]     ext_op,
    
    output reg  [`BUS_WIDTH] imm
);


    always @(*) begin
        if (rst) begin
            imm = `ZERO_WORD;
        end
        else begin 
            case (ext_op)
                3'b000: begin    // immI
                    imm = {{52{inst[31]}}, inst[31 : 20]};
                end
                3'b001: begin    // immU
                    imm = {{32{inst[31]}}, inst[31 : 12], 12'b0};
                end
                3'b010: begin    // immS
                    imm = {{52{inst[31]}}, inst[31 : 25], inst[11 : 7]};
                end
                3'b011: begin    // immB
                    imm = {{52{inst[31]}}, inst[7],       inst[30 : 25], inst[11 : 8], 1'b0};
                end
                3'b100: begin    // immJ
                    imm = {{44{inst[31]}}, inst[19 : 12], inst[20],      inst[30 : 21], 1'b0};
                end
                default: begin
                    imm  = `ZERO_WORD;
                end
            endcase
        end
    end

    
endmodule
